In certain prior art FPGA architectures, such as ACTEL 1010 (manufactured by ACTEL Corporation of Sunnyvale, Calif.), 2 logic modules are required to implement a flip-flop. This affects performance and gate utilization. In the ACTEL-1280 type of architectures, there are dedicated sequential blocks, flip-flops as part of the logic module. These flip-flops are uniformly distributed over the array, e.g. a typical array would have 400 combinational and 200 sequential logic modules. This limits the number of sequential blocks and combinational blocks that can be mapped, e.g. a design needing 300 combinational and 300 sequential elements cannot be mapped onto such an architecture. Also, a design with 500 combinational and 100 sequential blocks cannot be mapped onto such an architecture. Since the locations of sequential blocks is fixed on the array, it restricts the placement and routing efficiency. Instead if a free distribution positioning of sequential modules is allowed, it can give better layout optimization.
Therefore, it is an object of the present invention to provide an FPGA architecture wherein the sequential blocks are not dedicated on the array;
It is a another object of the present invention to provide an FPGA architecture wherein there is greater flexibility in mapping of combinational and sequential blocks.
It is a further object of the present invention to provide an FPGA architecture based on a single configureble logic module which can be configured to perform combinational or sequential functions.
These and other objects of the invention will become apparent to those of ordinary skill in the art having reference to the following specification, in conjunction with the drawings.